Microcode Generation for Flexible Parallel Target Architectures
Rainer Leupers, Wolfgang Schenk, Peter Marwedel · 1994
: Advanced architectural features of microprocessors like instruction level parallelism and pipelined functional hardware units require code generation techniques beyond the scope of traditional compilers. Additionally, recent design styles in the area of digital signal processing pose a strong demand for retargetable compilation. This paper presents an approach to code generation based on netlist descriptions of the target processor. The basic features of the MSSQ microcode compiler are outlined, and novel techniques for handling complex hardware modules and multi-cycle operations are presented. 1 Keyword Codes: B.1.4 Keywords: Control Structures and Microprogramming, Microprogram Design Aids 1 Introduction Besides instruction pipelining, two important means for increasing the throughput of microprocessors have been identified by hardware designers: instruction level parallelism and data pipelining. Instruction level parallelism comprises several functional units working independent...