A novel hierarchical multi-port cache
Z. Zhu, K. Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Toru Hironaka · 2004
A novel hierarchical multi-port cache is described in this paper, which implements the hierarchical multi-port memory architecture (HMA) based on 1-port banks. This type of cache has the advantages of high access bandwidth, low power dissipation and small area, which are studied and explained in detail. A test chip design of a 4-port HMA cache with 0.18/spl mu/m CMOS technology has been made.