System-MSPA design of H.263+ video encoder LSI for face focused videotelephony
Chawalit Honsawek, K. Ito, Tomohiko Ohtsuka, Tsuyoshi Isshiki, Dongju Li, Trio Adiono, Hiroaki Kunieda · 2002
In this paper, an LSI design for video encoder and decoder for H.263+ video compression with object based coding is presented. LSI operates under clock frequency of 27 MHz to compress QCIF(176/spl times/144 pixels) at the frame rate of 30 PB-frame per second. The core size is 4.5/spl times/4.5 mm/sup 2/ in a 0.35 /spl mu/m process. The architecture is based on bus connected heterogeneous dedicated modules, named as system MSPA architecture. It employs fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM. Design results achieve real time encoder in quite a compact size without losing flexibility and expandability. Real time emulation and easy test capability with external PC is also implemented.