A Design of a 8-Thread Graphics Processor Unit with Variable-Length Instructions
Kwang-Yeob Lee, Jae-Chang Kwak · Journal of information and communication convergence engineering · 2008
Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.