A verification logic representation of indeterministic signal states
Jody W. Gambles, Phillip J. Windley · NASA Technical Reports Server (NASA) · 1991
The integration of modern CAD tools with formal verification environments require translation from hardware description language to verification logic. A signal representation including both unknown state and a degree of strength indeterminacy is essential for the correct modeling of many VLSI circuit designs. A higher-order logic theory of indeterministic logic signals is presented.