Novel high-speed and low-power dynamic MOS flip-flops for a low-power 1.25GHz multiplexer/demultiplexer
Hiroshi Kanno, Takeshi H. Saito, Mayuko Sato · European Solid-State Circuits Conference · 1997
Novel high-speed and low-power dynamic MOS flip-flops have been developed. Simulation results show the newly developed flip-flop can operate 15% faster than the conventional flip-flop and dissipates 10% less current. To demonstrate the performance of the newly developed flip-flops, an 8-bit multiplexer/demultiplexer and divide-by-four dividers have been implemented in a 0.35um standard CMOS technology. The newly developed dynamic flip-flop was found to operate up to 2.8GHz and its reset type up to 2.2GHz. The maximum operating frequency of the 8-bit multiplexer/demultiplexer is 1.25GHz. It dissipates only 20mW. Its power-delay product is the lowest among all reported 8- bit multiplexer/demultiplexer core circuits to date.