An 80 b, 6.7 MFLOPS floating-point processor with vector/matrix instructions
Takashi Nakayama, Shingo Kojima, H. Harigai, Hiroshi Igarashi, K. Tamada, T. Toba · 2003
A description is given of an 80-b CMOS VLSI floating-point processor (FPP) in 1.2- mu m double-metal layer CMOS which contains 433000 transistors on an 11.6-mm*14.9-mm die. It operates at 20 MHz, dissipates 1.5 W, and is assembled in a 68-lead pin-grid-array package. The FPP is designed as a coprocessor for 32-b microprocessors. It implements data formats, arithmetic rounding modes, and exception types which are defined by the IEEE 754 standard. The chip can handle single (32 b), double (64 b), and double-extended (80 b) floating-point data formats. The complex-instruction-set-computer- (CISC-) like 78-instruction set includes 22 mathematical functions such as sin, cos, arctan, exp, and log, and 24 vector/matrix operations such as add, multiply, and inner product. The features and performance of the device are summarized.>