A Very High-speed FFT Device Architecture
S.A. White · 2005
A study was conducted to determine the maximum speed that could be coaxed from an FFT architecture using a pin-limited a rchitecture and an off-the-shelf technology. A radix-4 building block was selected, with on-chip distributedarithmetic t widdle-factor multipliers. A unique data-formatting scheme was developed which completely eliminated the c arry-propagatio n-delay problem. With 32 input-signal pins and 32 output signal pins, the four 16-bit real plus 1 6-bit imaginary data a re loaded in four clock cycles. The building blocks a re arrayed such that an epoch of data can be transformed every four clock cycles. The relationship between the device clock frequency, fc; the i nput-data sampling frequency, f,; and the number of points in the complex transform, N, is given by