VENUS - A Fully Automatic Design System for Complex Cell and Gate Array Chips
H. Vollmer, Klaus Blondin, B. Koch, Mélany Gutierrez Hernández, R. Müller · 1985
A semicustom VLSI design system is presented. Hierarchical chip designs of complexities up to 50.000 equivalent gates are supported when using parameterised general cells like RAM, ROM or PLA. The CAD tools of VENUS include automatic scan path routing, automatic placement and routing of general cells and test pattern generation.