Using IJTAG digital islands in analogue circuits to perform trim and test functions
Hans Martin von Staudt, Alexios D. Spyronasios · 2015
Demand for analogue precision and accuracy has significantly increased over the last few years, way beyond what the foundries can produce. At the same time short design cycles require the addition of digital configuration, trim, or assist functions to compensate for variation and uncertainties. Favourable configurations and trim values are then stored on chip in fuse arrays or OTP (One Time Programmable) as part of the test program. While such digital assist functions are generally viewed as cheap this is not necessarily the case in analogue heavy processes (130/180/250 nm). An additional constraint is the minimalistic digital interface to the tester, which is usually just an I2C interface. In this paper a scheme is described which utilises the recently introduced IJTAG standard (IEEE 1687) in an industrial environment. It allows the creation of digital islands close to the analogue circuit with minimal digital overhead. These IJTAG islands can hold the test and trim functions, which are distinct from the customer oriented use case. The mapping between I2C and IJTAG is transparent for the existing legacy test software and for the initialisation state machine which transfers the configuration and trim data from a central fuse or OTP block.