A highly-parallel DSP architecture for image recognition
Hiroyuki Kawai, Y. Inoue, R. Streitenberger, Masahiko Yoshimoto · 2002
The paper presents the architecture of a newly developed highly parallel DSP suited for realtime image recognition. The programmable DSP was designed for a variety of image recognition systems, such as computer vision systems, character recognition systems and others. The DSP consists of optimized functional units for image recognition: SIMD processing core, a hierarchical bus, address generation unit, data memories, DMAC, link unit, and control unit. The DSP can process a 5/spl times/5 spatial filtering for 512/spl times/512 images within 13.1 msec. Adopting the DSP to a Japanese character recognition system, the speed of 924 characters/sec can be achieved for feature extractions and feature vectors matchings. The DSP can be integrated in a 14.5/spl times/14.5 mm/sup 2/ single-chip, using 0.5 um CMOS technology. In the paper, the key features of the architecture and the new techniques enabling efficient operation of the eight parallel processing units are described. Estimation of the performance of the DSP is also presented.