URSA: A Unified ReSource Allocator for Registers and Functional Units in VLIW Architectures
David A. Berson, Rajiv Gupta, Mary Lou Soffa · 1993
The division of instruction scheduling and register allocation and assignment into separate phases can adversely affect the performance of these tasks and thus the quality of the code generated for load/store fine grained parallel architectures. Improved performance in one phase can deteriorate the performance of the other phase, possibly resulting in poorer overall performance. In this paper we present an approach that partitions instruction scheduling and register allocation and assignment into a new set of phases in an attempt to construct phases with minimal interaction. This approach uses a technique that unifies the problems of allocating registers and functional units. The technique, which consists of three phases, operates on a dependence DAG representation of the program. The first phase carries out the measurement of resource requirements and identifies regions with excess requirements. The second phase applies transformations that reduce the requirements to levels supported ...