Tracking radar digital matched-filter ASIC design and its error analysis
Zhenyu Liu Zhimei Zhou, Han Yue-qiu · Asia Pacific Conference on Circuits and Systems · 2003
The matched-filter is widely used in real time signal processing, especially in radar signal processing. This paper presents a novel structure of a digital tracking radar matched-filter, whose hardware overhead is one third of the traditional design but its throughput is doubled. With block-floating-point arithmetic, the precision is highly improved. The whole digital matched-filter is implemented in just one FPGA chip. This ASIC has two work modes: 512 points pulse compression and 256 points pulse compression. It complements three channels of 512 points complex signals in 102 /spl mu/s. The signal-to-noise ratio formula of this matched-filter is deduced at the end of the paper.