A CMOS RISC CPU with on-chip parallel cache
Ehsan Rashid, E. DeLano, K. Chan, M. Buckley, J. Zheng, Francis Schumacher, G. Kurpanek, J. Shelton, T. Alexander, N. Noordeen, Manfred Ludwig, A. Scherer, C. Amir, Dan Cheung, P. Sabada, Ram Rajamani, Nicholas S. Fiduccia, B. Ches, Kave Eshghi, F. Eatock · 2002
This CMOS CPU in a 0.55 /spl mu/m, 3-metal process integrates over 1.2 M transistors on a single chip. All circuitry on-chip operates at 140 MHz under typical conditions. All off-chip interfaces are cycled at the same frequency (with the exception of system bus interface, which is cycled at 120 MHz). Chip parameters are given.>