Network-on-Chip Architectures : A Holistic Design Exploration
Chrysostomos A. Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das · 2007
Abstract. Acknowledgments. 1. Introduction. 2. A Baseline NoC Architecture Part I MICRO-Architectural Exploratioin 3. ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers. 4. RoCo: The Row-Column Decoupled Router. 5. Exploring Fault-Tolerant Network-on-Chip Architectures. 6. On the Effects of Process Variation in Network-on-Chip Architectures. Part II MACRO-Architectural Exploration 7. The Quest for Scalable On-Chip Interconnection Networks. 8. Design and Management of 3D Chip Multiprocessors Using Network-In-Memory (NetInMem). 9. A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures. 10. Digest of Additional NoC MACRO-Architectural Research. 11. Conclusions & Future Work. References.