Adaptive FIR filter architectures for run-time reconfigurable FPGAs
Tero Rissa, R. Uusikartano, Jarkko T. Niittylahti · 2003
This paper presents a technique for realizing adaptive FIR filters that use constant-coefficient multipliers on a run-time reconfigurable FPGA. Three different adaptive FIR filter architectures for run-time reconfigurable FPGAs are presented. It is shown that run-time reconfigurable logic can be used to efficiently implement adaptive constant-coefficient FIR filters. With reasonable configuration latency, benefits in speed, area and power consumption are obtained.