A BIST methodology for at-speed testing of data communications transceivers
Shih-Chun Lin, Samiha Mourad, Shoba Krishnan · 2002
This paper discusses a new BIST methodology suitable for functional testing of transceivers on a data communications chip. Practical circuits are presented which allow the at-speed resting of various functional blocks. The concept has been applied to test a 400 Mbps 3-port IEEE 1394a system. The silicon for the 0.35 /spl mu/m CMOS implementation is expected in early 2001.