A 200 MHz internal/66 MHz external 64 kB embedded virtual three-port cache SRAM
Geordie Braceras, T. Frederick, Shawn A. Hall, Gary Koch, Robert McDonald, R. Purvee, R. F. Ross · 2002
A 66 MHz, 64 kB three-port cache SRAM has a 95 /spl mu/m/sup 2/ six-device cell and three internal pipelined accesses, allowing the single-port SRAM array to operate as a true multiported RAM. Using 0.8 /spl mu/m CMOS technology (Leff=0.45 /spl mu/m), the self-timed memory employs pipelined circuit techniques to independently access the array three times for every 15 ns processor cycle, two read/write processor accesses and one write-only memory access. The RAM is organized as 4 k/spl times/36/spl times/4 for processor interface, 2 k/spl times/288 for read memory port or storeback buffer (SBB), and 8 k/spl times/72 memory-write interface (reload buffer). Other features include cache line zeroing, four-way set associativity, byte-write controllability, port prioritization, address compare by-pass, array built-in self-test (ABIST), and byte alignment for misaligned memory accesses.>