A 90-MHz 16-Mb system integrated memory with direct interface to CPU
Katsumi Dosaka, Akira Yamazaki, N. Watanabe, H. Abe, J. Ohtani, T. Ogawa, K. Ishihara, Masaki Kumanoya · IEEE Journal of Solid-State Circuits · 1996
This paper describes a system integrated memory with direct interface to CPU which integrates an SRAM, a DRAM, and control circuitry, including a tag memory (TAG). This memory realizes a computer system without glue chips, and thus enables a computer system which is low cost, low power, and compact size, but still with sufficient performance. Also fast clock cycle time and access time is realized using a newly proposed clock driver and internal signal generator. This memory is fabricated with a quad-polysilicon double-metal 0.55-/spl mu/m CMOS process which is the same as used in a conventional 16-Mb DRAM. The chip size of 145.3 mm/sup 2/ is only a 12% increase over the conventional 16-Mb DRAM. The maximum operating frequency is 90-MHz and the operating current at cache-bit is 156-mA. This memory is suitable for various types of computer systems such as personal digital assistants (PDA's), personal computer systems, and embedded controller applications.