RTL synthesis for systolic arrays
William Robertson, Shalini Periyalwar, William Phillips · 1993 IEEE International Symposium on Circuits and Systems · 2002
A register-transfer-level systolic synthesis strategy for multidimensional systolic arrays is described. Optimum utilization of silicon is attained by rescheduling operations on functional units across processing elements. The synthesis tool examines the tradeoff between sharing of functional units, additional buses, and the size of the controller.>