Scan-based transition fault testing - implementation and low cost test challenges
J. Saxena, Kenneth M. Butler, J. Gatt, Ramanan Raghuraman, Sahu Pratap Kumar, Sukla Basu, David J. Campbell, J. Berech · 2003
The semiconductor industry as a whole is growing increasingly concerned about the possible presence of delay-inducing defects. There exist structured test generation and application techniques which can detect them, but there are many practical issues associated with their use. These problems are particularly acute when using low cost test equipment. In this paper, we describe an overall approach for implementing scan-based delay testing with emphasis on low-cost test.