A new RNS architecture for the computation of the scaled 2D-DCT on field-programmable logic
P. García‐Fernández, Javier Ramı́rez, Antonio García, Luis Parrilla, A. Lloris · 2002
This paper shows the implementation of an 8/spl times/8 scaled two-dimensional Discrete Cosine Transform processor (2D-DCT) based on the Residue Number System (RNS). The row-column decomposition technique is used and each 1D-DCT processor has been derived by the application of a previously developed scaled Fast Cosine Transform (FCT) algorithm that requires a reduced number of multiplications. Simulations of binary 2's complement and RNS version of the scaled 2D-DCT processor using VHDL over Field-Programmable Logic (FPL) devices provide a throughput improvement for the proposed RNS-based 2D-DCT processor of up to 148% when 8-bit moduli are used. This is achieved due to the synergy between RNS and modern FPL device families.