System-level timing analysis and scheduling for embedded packet processors
Samarjit Chakraborty · 2003
Packet processors are high-performance, programmable devices with special architectural features that are optimized for network packet processing. They are mostly embedded within network routers and switches and are designed to implement complex packet processing tasks at high line speeds. In this thesis we study several issues related to system-level timing analysis and scheduling for such embedded packet processors. Our work is motivated by the fact that designing and analysing the hardware-software architectures for packet processors require new models and methods which do not fall within the preview of traditionally studied embedded systems.