The formal verification chain at BULL
J.C. Madre, Olivier Coudert, M. Currat, Alain Debreil, Christian Berthet · 2002
Presents the chain of tools developed at BULL for the verification of circuit designs. For several years, BULL has been a leading site in the field of formal verification of hardware. Until now, the main concern of BULL was in the validation of the VLSI circuits of its mainframe CPUs. The effort is currently extended to board components such as PLDs and ASICs.>