Best Practices for Compact Modeling in Verilog-A
Colin C. McAndrew, Geoffrey J. Coram, Kiran K. Gullapalli, J. Robert Jones, Laurence W. Nagel, A. Roy, Jaijeet Roychowdhury, A.J. Scholten, Geert D. J. Smit, Xufeng Wang, Sadayuki Yoshitomi · IEEE Journal of the Electron Devices Society · 2015
Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.