Implementation of multiple-valued multiplier on GF(3/sup m/) using current mode CMOS
Hyeon Kyeong Seong, Jai Seok Choi, Boo Sik Shin, Heung Soo Kim · 2002
The multiplication algorithm of two polynomials on finite fields GF(3/sup m/) is presented. The 3-valued multiplier of the serial-in/parallel-out modular structures on GF(3/sup 3/) to be performed on the presented multiplication algorithm is implemented by current-mode CMOS. The current-mode CMOS 3-valued multiplier is implemented two GF(3) multipliers and two GF(3) adders. Performances of the proposed circuits are evaluated using Pspice simulations with 2.0 /spl mu/m standard CMOS device parameters, 20 /spl mu/A unit current level and 3.3 V V/sub DD/ voltage supply.