Network-on-Chip (NoC) Topologies and Performance: A Review
Jie Chen, Paul Gillard, Cheng Li · 2011
With the development of integration technology, System-on-Chip (SoC), composed of heterogeneous cores on a single chip, has entered the billion-transistor era. As the microprocessor industry moves from single-core to multi-core, and eventually to many-core architectures, containing tens to hundreds of similar cores arranged on a single multiprocessor chip requires efficient communication among processors. A highperformance, flexible, scalable, and design-friendly interconnection architecture is highly desired for modern SoC and microprocessor designs. How to provide efficient communication poses a challenge to both academia and industry. Before the advent of Network-on-Chip (NoC), interconnection architectures were usually based on dedicated wires or shared buses. However, they cannot meet the ever-increasing demand from the onchip systems due to the lack of scalability. NoC has been proposed as a highly structured and scalable solution to address the communication problems in on-chip systems. NoC has several advantages over dedicated wiring and buses, e.g., highbandwidth, low-latency, low-power consumption and scalability. Messages are transported back and forth via the interconnection networks. Thus, the interconnections among multiple cores on a chip have a significant impact on communication and performance of the chip design in terms of end-to-end delay, throughput, and packets loss ratio. Therefore, it is worthwhile studying the different characteristics of different topologies. In this paper, we review the most popular topologies and also some recent topologies for interconnection networks. We study their performance and summarize their strengths and limitations.