A delay-encoding-logic array processor for dynamic programming matching
Makoto Ogawa, T. Shibata · 2004
Computationally very expensive, dynamic programming matching of data sequences has been directly implemented as a fully-parallel-architecture VLSI chip. The chip is organized as a 2D array of delay-encoding logic units, which works as an automatic best-match-sequence search network. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain. As a result, high-speed low-power operation has been established with a small chip area. A prototype chip was designed and fabricated in a 0.18-/spl mu/m CMOS technology, and a typical matching time of 80 ns with a power dissipation of 2 mW under a 1.3 V power supply has been demonstrated.