A systolic array algorithm for an efficient unified memory-based implementation of the inverse discrete cosine and sine transforms
Doru Florin Chiper · 1999
This paper presents a new design approach for a memory-based VLSI implementation of IDCT and lDST transforms. This approach is based on a new systolic array algorithm that uses a highly modular and regular computational structure as circular convolution and can be used to obtain a highly efficient unified VLSI chip for both IDCT and IDST with very little silicon area unused for a specific transform. The new VLSI algorithm has two half-length circular convolutions with the same length and structure which can be concurrently computed and such reformulated that an efficient substitution of multipliers with small ROM's can be obtained. Moreover, due to the fact that the content of the two ROM's in the same processing element is the same, a substantial reduction in the hardware cost can be obtained using biport ROMs.