Contention on 2nd Level Cache May Limit the Effectiveness of Simultaneous Multithreading
S. Hily, André Seznec · 1997
: Simultaneous multithreading (SMT) is an interesting way of maximizing performance by enhancing processor utilization. We investigate issues involving the behavior of the memory hierarchy with SMT. First, we show that ignoring L2 cache contention leads to strongly over-estimate the performance one can expect and may lead to incorrect conclusions. We then explore the impact of various memory hierarchy parameters. We show that the number of supported threads has to be set-up according to the cache size, that the L1 caches have to be associative and small blocks have to be used. Then, the hardware constraints put on the design of memory hierarchies should limit the interest of SMT to a few threads. Key-words: multithreading, simultaneous multithreading, cache hierarchy (R'esum'e : tsvp) Les travaux de S'ebastien Hily sont en partie financ'es par la r'egion Bretagne [email protected], [email protected] Unite de recherche INRIA Rennes IRISA, Campus universitaire de Beaulieu, 35042 RENNES Ce...