A 40ns 64Mb DRAM With Current-sensing Data-bus Amplifier
M. Taguchi, H. Tomita, T. Uchida, Yoshitaka Oonishi, Keita Sato, Taiji Ema, Masaaki Higashitani, Kenji Nakagawa, Masahiro Kanazawa, T. Yabu · 1991
This 64Mb DRAM with a current-sensing data bus amplifier combined with bus-line-on-cell chip architecture provides parallel wide-band data processing of 64b compressed test functions. Column-select lines are separated for read and write operations to enable immediate operation change. In ad dition, sense amplifiers are isolated from data bus lines so that column selection can be independent of sense amplifier activa tion timing. 40ns typical RAS access time is obtained.