A single chip 80b floating point processor
Kouhei TAKEDA, F. Ishino, Yasuaki Ito, Ryota Kasai, Takayoshi Nakashima · 1985
The application of 1.2μ N-well CMOS technology in a 5.6 MFLOP 80b floating-point processor chip will be described. The chip, which includes 50K gates and 15Kb of memory, was designed, in 11 man months with a heirarchical design automation system.