An 800MHz star-connected on-chip network for application to systems on a chip
Se-Joong Lee, Seong-Jun Song, Kangmin Lee, Jeong‐Ho Woo, Sung-Eun Kim, Byeong‐Gyu Nam, Hoi‐Jun Yoo · 2003
A 10.8/spl times/6.0mm/sup 2/ prototype chip is implemented with a star-connected on-chip network. The chip consists of a PLL, 1KB SRAM, two 2/spl times/2 crossbar switches, Up/Down-Samplers, two off-chip gateways, and synchronizers. The on-chip network contains 81k transistors, dissipates 264mW at 2.3V and 800MHz, and provides 1.6GB/s per port and 12.8GB/s aggregated bandwidth, supporting plesiochronous communication without global synchronization.