The design and implementation of a first-generation CELL processor
D. Pham, Saki Asano, M. Bolliger, Michael Day, H. Peter Hofstee, Charles Johns, J. Kahle, Atsushi Kameyama, J. Keaty, Yoshio Masubuchi, M. Riley, D. J. Shippy, Daniel Stasiak, M. Suzuoki, Mingjun Wang, James N. Warnock, S. Weitzel, D. Wendel, Taro Yamazaki, Kazuaki Yazawa · 2005
A CELL processor is a multi-core chip consisting of a 64b power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high-frequency clock-rate.