A floating-point systolic array processing element using serial communication
Trevor Davies, D. Al-Khalili, Valek Szwarc · 2002
The authors describe the design of a processing element (PE) for systolic array applications. The PE which is configured as a multiplier-accumulator or an inner product step processor, supports most common systolic algorithms in signal processing and matrix arithmetic. Communication with neighbouring PEs is achieved through 18 on-chip serial links, each operating at 50 Mb per second. The 30 K transistor ASIC device is implemented in 2 micron HCMOS gate array technology, packaged in a 48 pin DIP and performs at 10 MFLOPS.>