BBCS Based Sparse Matrix-Vector Multiplication: Initial Evaluation
Simon Vassiliadis, Sorin Cotöfană, Pyrrhos Stathis · 2000
This paper presents an evaluation of the BBCS scheme meant to alleviate the performance degradation experienced byVector Processors (VPs) when manipulating sparse matrices. In particular we address the execution of Sparse Matrix Vector Multiplication (SMVM) algorithms on VPs. First weintroduce a Block Based Compressed Storage (BBCS) sparse matrix representation format variants, and a BBCS based SMVM algorithm. Subsequently, we consider a set of benchmark matrices, report some preliminary performance evaluations, and compare our scheme with the Jagged Diagonal (JD) scheme. Our experiments suggest that our scheme achieves an average vector register filling larger then the one achieved by JD and that is not sensitive to the assumed value of the VP section size. Due to reduction of the startup penalty when executing vector instructions, higher vector register filling will translate into higher performance. 1