Maps: a compiler-managed memory system for software-exposed architectures
Rajeev K. Barua, Saman P. Amarasinghe, Anant K. Agarwal · DSpace@MIT (Massachusetts Institute of Technology) · 2000
Microprocessors must exploit both instruction-level parallelism (ILP) and memory parallelism for high performance. Sophisticated techniques for ILP have boosted the ability of modern-day microprocessors to exploit ILP when available. Unfortunately, impro