FILU-200 DSP coprocessor IP core
Chris J. Bleakley, V. Berg, Jorge Quintás Rodríguez, B. Murray · 2003
Massana's FILU-200 DSP coprocessor IP core enables fast development of DSP in embedded applications. The FILU-200's library of pre-programmed DSP functions are accessed via C function calls from a host RISC processor. The FILU-200 matches high-end DSPs for MIPS capability at a fraction of the silicon cost. The dual MAC architecture with dual ALU, and dual barrel shifter is tailored for highest DSP performance in small silicon area. The FILU-200 is particularly suited to fast complex number arithmetic yielding a radix-4 FFT butterfly in 8 cycles, i.e. 1024-point complex FFT in 103 /spl mu/s. Near floating point precision is supplied by block floating point arithmetic combined with a 20-bit internal data path. Optimized building block DSP functions, including FFT, IFFT, FIR filters, IIR filters and matrix operations, are microcoded in ROM and are supplied with the FILU-200. The small silicon area of the FILU-200, 30 K gates, enables its adoption in cost sensitive applications. Typical applications include soft modems, G.Lite, DAB, VoIP and audio.