Implementation of JPEG2000 arithmetic decoder on a dynamically reconfigurable ATMEL FPGA
Sophie Bouchoux, El‐Bay Bourennane, Johel Mitéran, Michel Paindavoine · IEEE Computer Society Annual Symposium on VLSI · 2004
This paper is about the implementation of a part of the JPEG2000 algorithm (MQ-decoder and arithmetic decoder) in a FPGA by using dynamic reconfiguration. The implementation is done on an architecture named ARDOISE, created to study fine grain dynamic reconfiguration of FPGAs.