A 1M synapse self-learning digital neural network chip
Osamu Saitô, Kimihisa Aihara, Osamu Fujita, K. Uchimura · 2002
New neural network chip architectures that can process neural networks with large-capacity synapse weight in real time are needed to solve real-world problems. Conventional digital neurochips achieve high-speed operation by parallelizing processing on the premise that synapse weights are stored in on-chip memory and can be accessed at high speed. This premise restricts the size of a network and therefore the size of the problem that the chip can handle. To solve this problem, this digital neural network chip uses sparse memory-access (SMA) architecture to eliminate unnecessary external memory access. The chip, together with sixteen 1 Mb external SRAMs, handles a 1M synapse network, 50 times larger than a conventional on-chip memory-based neural network chip can handle. An external RAM access mechanism enables high-speed calculation using data stored in external memory. High-speed on-chip learning using SMA is implemented, another major advantage over previous chips.