A cost-oriented two-port unified cache for low-power RISC microprocessors
Hiroyuki Mizuno, Koji Ishibashi · 2002
Inexpensive implementation of a two-ported unified cache by using a separated bit-line memory hierarchy architecture is proposed for low-cost microprocessor applications. The same bit-rate as with conventional separated caches can be realized while the size can be reduced by 40% with capacity of more than 64 KB. The cache is physically addressable and achieves 4.2 ns latency.