Programmable at-speed array and functional BIST for embedded DRAM LSI
M. Kume, Keijiro Uehara, M. Itakura, Hideo Sawamoto, Takashi Kobayashi, M. Hasegawa, Hideki Hayashi · 2005
A new approach to DFT (design for test) for an embedded DRAM LSI is proposed in This work. One powerful BIST engine is implemented on the LSI, which executes not only the array BIST for the DRAM and SRAM macros, but also functional BIST for the whole chip. It was implemented in an embedded DRAM cache LSI which is presented together with measured results.