Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays
Sebastian Siegel, Renate Merker · Parallel Computing in Electrical Engineering · 2004
This paper describes a method for algorithm partitioning through which affine indexed algorithms are transformed to Processor Arrays. Former design flows start with a spacetime transformation which we omit completely. Therefore, we are able to consider the constraints of a target architecture at the beginning of our design flow. We show our method for three different partitioning schemes and emphasize on the derivation of a schedule. The principle of an optimized data-reuse is introduced for our partitioning methodology. Under this aspect, we give a parameterized Processor Array for the 2D FIR filter algorithm.