Packet Dispatching Schemes for Three-Stage Buffered Clos-Network Switches
Janusz Kleban · InTech eBooks · 2009
Switching fabric CPU Interface Ingress line card Egress line card CPU Interface CPU Interface CPU Interface 0 1 2 3 0 1 2 3 Collision 0 3 Output's number 1 www.intechopen.comVOQ(0,0,0) VOQ(0,k-1,n-1) IP (0,0) IP (0,n-1) IM (0) VOQ(i,0,0) VOQ(i,k-1,n-1) IP (i,0) IP (i,n-1) IM (i) VOQ(k-1,0,0) VOQ(k-1,k-1,n-1) IP (k-1,0) IP (k-1,n-1) IM (k-1) CM (0) OM (0) CM (r) OM (j) CM (m-1) OM (k-1) LI (i, r) LC (r, j) OP (0,0) OP (0,n-1) OP (j,0) OP (j,n-1) OP (k-1,0) OP (k-1,n-1) How to referenceIn order to correctly reference this scholarly work, feel free to copy and paste the following: