SystemC-based Custom Reconfigurable Cores for Wireless Applications.
Ali Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan · ERSA · 2008
There is a significant demand for embedding high performance reconfigurable cores within future system on chip (SoC) designs as such cores offer flexibility as well as superior performance advantages in terms of speed, power and run time reconfigurability. However, one obstacle to the adoption of such cores within SoC designs is lack of know-how on how to model such high performance cores such that they can be exploited by electronic system level (ESL) design tools and methodologies. This paper proposes a new multi-context representation in order to capture reconfigurable features, within different embedded reconfigurable cores, at different run time periods. A cosimulation framework is proposed as part of the design and modelling procedure. A hybrid SystemC-HDL co-simulation scenario is utilised in order to demonstrate interoperability of the designed reconfigurable hardware block. As a case study, we utilise our modelling strategy in order to design the crucial WiMAX standard compliant telecommunication receiver where two new reconfigurable fabrics are employed for the implementation of the performance bottlenecks within this standard, namely FFT and Viterbi processing tasks. We demonstrate how our modelling approach can be utilised to capture complete system functionality and provide performance and power consumption figures for system design.