Cache Coherence Protocols for Many-Core CMPs
Alberto Ros, Eduardo Gando Manuel, José María · InTech eBooks · 2010
Multi-core architectures have emerged as the best alternative to take advantage of the increas-ing number of transistors currently offered in a single die. For example, the dual-core IBM Power6 (Le et al., 2007) and the eight-core Sun UltraSPARC T2 (Shah et al., 2007) have a rela-tively small number of cores, which are typically connected through a shared medium, i.e., a