A 3.2 GOPS multiprocessor DSP for communication applications
J. Williams, K.J. Singh, Chris Nicol, Eduard Säckinger, S.J. Daubert, E. Micca, M. Moturi, Jens Knobloch, D.M. Brinthaupt, Bryan D. Ackland · 2002
This programmable DSP is the first implementation of the scaleable-bus-based platform, Daytona for communication infrastructure equipment and broadband access terminals. An aggressive memory hierarchy minimizes bus traffic and meets the performance requirements for large multi-channel signal processing applications with the smallest possible memory footprint. The chip was implemented with full custom memories with 0.35 /spl mu/m features and the remaining logic is implemented with standard cells. The 207 mm/sup 2/ 0.25 /spl mu/m CMOS chip achieves 100 MHz and dissipates 4 W at 3.3 V.