Testing the logic cells and interconnect resources for FPGAs
Abderrahim Doumar, Hideo Ito · 2003
This paper presents a new design for testing SRAM based field programmable gate arrays (FPGAs). The new proposed method is able to test both the configurable logic blocks (CLBs) and the interconnection networks. The proposed design is based on slightly modifying the original SRAM part in the FPGA so that it will allow the configuration data to be looped on a chip and then the test becomes easier. This method requires a very short test time compared to the previous works. Moreover, the off-chip memory used in the storage of the configurations data is considerably reduced. The application of this method to the XC4000 family and ORCA shows that (relative to that required by the previous works) the test time can be reduced by 87.2% and the required off-chip memory can be reduced by 88.6%.