Modeling and verification of a pipelined CPU
Lubomir Ivanov · 2003
In this paper, we present a formal model of a pipelined version of the DLX processor, and verify the correct operation of the pipeline using a formal verification approach based series-parallel posets. We illustrate how the method can be used to detect pipeline hazards and other problems. The full verification was carried out automatically with the help of a verification tool, based on algorithms with low time- and space complexity.