A testable CMOS signal processor for fast Fourier transforms
N.A. Ramakrishna, M.A. Boyoumi · 2003
The authors present the architecture of a fast Fourier transform processor which has high performance characteristics and an embedded test structure that allows the processor to test itself during normal operation. The properties of separable residue codes have been used for error detection in the arithmetic unit of the processor. Offline error detection which tests for the classic stuck at faults is based on the properties of the dynamic CMOS logic design used. The testing circuitry used in the architecture accounts for only a 20% area overhead and no time ahead, an important saving in a signal-processing environment.>